Spartan-6 FPGA Connectivity Targeted Reference Design Performance

This white paper summarizes performance as measured on the Spartan-6 FPGA Connectivity targeted reference design available with the Spartan-6 FPGA Connectivity Kit.

The results clearly demonstrate that:

• Throughput scales with variation in packet size.

• PCI Express performance improves with higher maximum payload size.

• CPU utilization improves with checksum offloading.

• An inverse relationship exists between packet size and CPU utilization.

The Spartan-6 FPGA Connectivity targeted reference design provides a high-quality, fully validated, and performance-profiled system that can help jump start end user development, thereby reducing time to market.