Archives: Articles
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IP for Complex FPGAs
According to Gartner’s Jim Tulley, there are around 7,000 ASIC design starts a year, a number that is in slow decline. By way of contrast,…
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Uncanny Resemblances
If you had all the time in the world, you could simulate an entire SoC using SPICE, but you don’t, so you can’t. At least…
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Is Free Too Good to be True?
A few weeks ago I wrote about model-based development in Modelling: not just for big boys? At the end of the article I said “So…
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Deep and Wide
We engineers are unusually comfortable with periodicity. We find ourselves fooling around with frequency domain from the first days of our undergraduate education, and by…
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Getting Around Limits By Getting High
If you were able to record the development of a town as it grew into a city over years and decades and then speed up…
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Toys for Engineers in Automotive
There is an old story about two shoe sales people sent to a desert island. The first looks around and sends a message back to…
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Minimizing the Pain of RTL Design Reviews
Design reviews conger images of engineers carrying reams of code printouts, filing single-file and head down into a room to be judged by others. The…
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HardCopy in Practice
Altera has carved a unique niche in the market with their HardCopy ASIC offering. As we all know, FPGAs offer some compelling benefits when compared…
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Entering the Spin Zone
Some time back we took a brief look at MRAM technology, mostly from the standpoint of contrasting it with FRAMs, triggered by a specific paper…
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Hooking Up
The number of options for getting from point A to point B keeps growing. It’s one of those areas where the concept of “standard” is…