Archives: Articles
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Renaissance FAEs
In classical music, they are the organists. My brother, an accomplished professional trumpet player, had just completed a performance for solo piccolo trumpet and organ. …
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Going Back to the Formal
Back a decade or so ago, there was a big hoo-hah about “formal verification.” Things burned hot for a while, then cooled down and more…
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Two Chips Or One?
A few years ago when SERDES became available on FPGAs, they were exotic. Both for the FPGA guys and for their users. The FPGA guys…
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Displaying the Future
To see the future of embedded design, all we have to do is watch Tom Cruise. Partway through “Minority Report,” the actor waves his hands…
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Faster Space Exploration
In yet another installment of how life has gotten complicated in the design-for-manufacturing (or design-for-yield) world, we re-enter the world of the modern designer as…
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A Passel of Processors
Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize…
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A Passel of Processors
Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize…
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Broken Design Flows and Point Tools
Where do you go for help when your design flow is broken? Wally Rhines of Mentor Graphics wants it to be to him and his…
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Shortening the Rope
Once upon a time, a man was given a rope and was told that it would be useful for many things. That most anything could…
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Performance Improvements with New Secure IP and FAST Simulation Mode Models
Today’s high-capacity and high-performance FPGA designs are becoming more complex and require more third-party intellectual property (IP) cores. These hard IP blocks include pecialized high-speed…