Archives: Articles
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40nm Altera Stratix IV
New process nodes have a predictable rhythm. Until about 90nm, we knew before anybody announced anything that we’d get double the density, half the power…
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Special Recognition
“OK people, can I have your attention please? I need you all to listen up. All right. Quiet… Now… I want you all to get…
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Three Chords and the Truth
Twelve Bar Blues is structured improvisation. A standard twelve-measure chord progression repeats tirelessly, and the experienced blues musician lays his soul over this monotonous harmonic…
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High-Speed Serial Comes to the Analog/Digital Divide
Everyone knows that if you want to do things slowly, you do them one at a time. If you want to get more done, you…
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Multicore Messaging Manifested
A few weeks ago we took a look at the new MCAPI standard that provides low-level, low-overhead message-passing capabilities for multicore and tightly-coupled multi-processor systems.…
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Avoiding Failure Analysis Paralysis
Back when I was a product engineer working on bipolar PALs (oops – I mean, PAL® devices), one of my main activities was figuring out…
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Golden Hammer
The countdown counter/timer circuit was pretty trivial to code up in VHDL. My dev board had an old FPGA on it, but it didn’t matter. …
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Coming to a Home Near You?
This is a story that starts with the improbable topic of building controls – you know, those complex systems that ensure that no matter where…
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Almost Instant Replay
It’s 4th and goal, 0:15 to go in the last quarter. The ball is snapped, the quarterback steps back, finds his receiver, and throws. Seeing…
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How To Implement SystemVerilog for FPGA Design
Introduction Since its ratification in 2005, the SystemVerilog IEEE-1800 standard has experienced broad adoption in the verification and assertion space but has lagged for design…