Archives: Articles
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Power Exploration in High-Level Synthesis
Area optimization and timing closure have long been considered the most common digital design challenges in mainstream digital IC design. Much has been analyzed and…
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Dangling Propositions
Every year, we put on our historian hats and look back at the events of the previous twelve months. (It turns out that our historian…
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System Management – Not Sexy, But Critical
Your boss begins to drone on about the system maintenance check list items during your weekly meeting. Power initialization and sequencing, reset management, voltage and…
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A Techfocus Tribute
“FPGA’s at this price point offer an unprecedented value, and are an excellent strategy to future-proof your design with.” Shirley stares at the sentence glowing…
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Is There a Database in Your Future?
From one point of view, the embedded developer is the major obstacle that stands between the marketing guy’s vision of that cool new product and…
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Success with System Simulation
As a private pilot, I’m well acquainted with the benefits of simulation. With a light plane, it’s pretty clear. You can virtually fly for hours…
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Unified FPGA-ASIC Design Flow Provides Designers Versatility in Meeting Production Goals
Today’s fast-paced chip delivery schedules require that logic designers employ design flows that are versatile enough to take advantage of several implementation technologies. Specification changes,…
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Pins for Pennies
The low-cost FPGA battle is now officially on fire. Not that long ago, the FPGA race was two-dimensional – whoever could provide the most programmable…
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The New DSP
On the fading footsteps of the fury of the Supercomputing conference, our minds typically whirl on the world of accelerated computation. We picture powerful systems…
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The Secret
“…It works the same as assertions in System Verilog,” he said. I quickly nodded my head — maybe too quickly. “Oh, OK, I see,” I…