Archives: Articles

  • What’s Your Persona?

    What’s Your Persona?

    Unbelievable! FPGA Journal is running a feature article on a Xilinx organization change? What’s next, an exposé on Altera’s new carpets at corporate headquarters? Maybe…

  • Jason Cong

    Jason Cong

    Professor Jason Cong’s office on the campus of UCLA is full, but not cluttered; important, but not pretentious; functional, but not over-designed. A wall of…

  • FPGA-PCB Co-Design – More Than Just Data Transfer

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  • Methodology Melting Pot

    Methodology Melting Pot

    The first explorers came with Karnaugh maps and truth tables. Complex combinational functions could be concentrated in programmable logic devices more efficiently than with random…

  • Advancing FPGA Design Efficiency: A Proven Standard Solution

    Advancing FPGA Design Efficiency: A Proven Standard Solution

    For decades the SoC design community has consistently lost ground in the battle to match advances in design technology productivity with the growth of available…

  • Digital Do-Overs

    Digital Do-Overs

    His eyes meet the goalie’s steely gaze. He refuses to be stared down. In his mind, he calmly visualizes the moves to come, picturing success…

  • FPGA I/O Features Help Lower Overall PCB Costs

    FPGA I/O Features Help Lower Overall PCB Costs

    Introduction High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several…

  • FPGA I/O

    FPGA I/O

    Over the past decade, FPGAs have gained a foothold as one of the most used building blocks in digital systems. The flexibility of an FPGA…

  • FPGAs in Space

    FPGAs in Space

    When was the last time you disassembled the package of each FPGA in your design to make sure the bonding is secure? Would your design…

  • The Challenges of Modern FPGA Design Verification

    The Challenges of Modern FPGA Design Verification

    Fifteen years ago verification of FPGA designs was easy: you only needed a decent gate-level simulator to verify a circuit containing several thousands of logic…