Archives: Articles
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Xilinx Goes Retro
All the FPGA action these days is in the new, emerging markets right? As we’ve all discussed for awhile, CPLDs are a nice steady market…
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Semi-Programmable
It stands to reason. Some components of system-on-chip design are static. You’re not going back and re-engineering them every two weeks. The multiplier was designed…
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Cool and Groovy at DAC
I have now attended more than half of the 41 annual Design Automation Conferences. One of the things I’ve noticed during those twenty-odd years is…
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DAC’s Dangerous Undertones
The 41st Design Automation Conference in San Diego last week wasn’t a bad conference. In fact, it was quite a good one. According to the…
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Racing for the Gap
As suppliers jockey for position in offering products that hit the gap between the flexibility and risk-free design offered by FPGA and the performance and…
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Virtex-4
In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that…
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Leveraging On-Chip Debug for VME
Introduction Galileo Avionica needed an easy-to-use VME BUS monitor that could be used by both hardware and software engineers working on VME-based projects. Using a…
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Catapult C
Electronic design automation has its own secret little cold fusion. An innovation that everyone quietly hopes is possible but publicly disavows. A development that would…
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FPGA Simulation
When someone uses the words “verification” and “FPGA” in the same sentence, I’m always suspicious. In the ASIC design world, where risk avoidance is everything,…