Would you buy a $20 GateMate FPGA from Germany’s Cologne Chip?

My good friend Adam Taylor recently published a couple of blogs about a new-to-me FPGA vendor named Cologne Chip, a 25-year veteran semiconductor vendor. The company was founded in 1994 as Cologne Chip Designs, and back then, it focused on developing ASICs for the nascent ISDN market. ISDN, or the Integrated Services Digital Network, was the telecom industry’s early effort to develop a digital standard interconnect for telephone systems. Within two years, Cologne Chip Designs had introduced its first ISDN chip. (ISDN standardization took so long that the four-letter abbreviation came to be reinterpreted as “I still don’t know,” “I see dollars now,” or the “innovation that subscribers don’t need.” Eventually, broadband Internet killed ISDN.) Cologne Chip Designs subsequently entered other markets by developing a PCMCIA interface chip and a USB chip. In the year 2000, the company renamed itself Cologne Chip AG and, five years later, expanded into IP design for ASIC development. Cologne Chip introduced its line of small and mid-sized GateMate FPGAs in 2020, but the company had accumulated more than three decades of chip-manufacturing expertise by then.

Like most FPGA vendors except Intel, Cologne Chip is a fabless semiconductor vendor. (Intel’s own fabs make the silicon die for the company’s most advanced FPGAs, while other foundries make the silicon used in Intel’s older FPGAs.) Globalfoundries manufactures Cologne Chip’s FPGAs in a 28nm SLP (Super Low Power) process technology, which makes these FPGAs comparable to AMD’s Spartan 7 and Artix 7 FPGAs and Intel’s Cyclone V FPGAs.

The fundamental logic cell in a Cologne Chip GateMate FPGA is a CPE (Cologne Programmable Element), which can be field-configured as one 8-input lookup table (LUT), a dual 4-input LUT, a 4-input multiplexer, a cascadable 1- or 2-bit full adder, or a cascadable 2×2-bit multiplier. Each CPE also contains two flip-flops. The GateMate FPGA fabric also incorporates dual-ported SRAMs (DPSRAMs), commonly called Block RAMs (BRAMs), which can be configured as one 40-kbit or two 20-kbit RAM blocks. The GateMate FPGAs do not include hardened DSP blocks as do FPGAs from many other FPGA vendors, but you can build DSP blocks using variously configured CPEs.

One other thing you will not find in any GateMate FPGA is a hardened microprocessor core. In that respect, and with the lack of DSP blocks, GateMate FPGA architecture reminds me more of FPGAs from the 20^th century than an FPGA from the 21^st century, with the caveat that Cologne Chip’s 28nm FPGAs are very much a part of the current century. The lack of hardened processor cores and DSPs is not necessarily a bad thing. Many designers prefer to use “pure” FPGAs – incorporating only programmable logic – in their designs.

The GateMate FPGAs also incorporate one or more SerDes transceivers capable of operating at either 2.5 or 5 Gbps. (The documentation isn’t consistent about the SerDes bit rate.) Like most contemporary FPGAs, Cologne Chip’s GateMate FPGAs employ SRAM-based configuration and load their configuration bitstream from an external EEPROM or some other external device at boot time through an SPI or a JTAG port.

Cologne Chip’s GateMate FPGA data sheet lists six family members with 20,480 to 512,000 CPEs, but as far as I can tell from the documentation, the company has only manufactured the smallest two family members with 20,480 CPEs, 64 20-kbit (configurable as 32 40-kbit) BRAMs, and one SerDes transceiver or 40,960 CPEs, 128 BRAMs, and two SerDes transceivers. According to the data sheet, the company may also be in production with the next largest GateMate family member with 81,920 CPEs, 256 BRAMs, and two SerDes transceivers. In today’s FPGA world, these are relatively small FPGAs.

One of the GateMate FPGA’s unique characteristics is its development tool chain, which is largely based on open-source tools such as Yosys open synthesis suite and OpenFPGALoader. Cologne Chip developed a proprietary bitstream generator, which is consistent with other FPGA vendors, because FPGA vendors are loath to reveal the routing structures and other secrets of their chip designs and open place-and-route tools would bare all. These tools employ a command-line interface. No fancy GUI here.

Cologne Chip provides pre-built, downloadable development tool packages containing binaries for all tools in the chain and sample projects. According to Adam Taylor, these pre-built packages are only 25 Mbytes or so in size, which is much smaller than the multi-Gigabyte tool chain downloads offered by the major FPGA vendors. Discussions of the GateMate tool chain often carry enthusiastic remarks about the “free” development software, but the major commercial FPGA vendors generally offer free editions of their tools for their smaller FPGAs anyway, so I’m at a loss to see much of an advantage in these open tools, other than the obvious religious trappings associated with open-source advocates who might be tempted to gloss over the proprietary, non-open nature of Cologne Chip’s place-and-route tools, which sit at the very heart of the tool chain.

Cologne Chip offers a GateMate Evaluation Board that incorporates a GateMate A1 FPGA, the smallest member of the GateMate FPGA family, with 20,480 CPEs. In addition, the board has USB configuration and power ports, two Pmod ports, an SMA connector carrying the FPGA’s solitary SerDes transceiver port, and 108 GPIO pins on six connectors associated with six of the GateMate A1 FPGA’s eight GPIO banks. Memory on the evaluation board includes a 64-Mbit SPI Flash EEPROM for configuration data and a 64-Mbit HyperRAM chip. In the US, the Cologne Chip GateMate Evaluation Board is available from Digi-Key for $81.25. Just this month, Trenz Electronic announced a low-cost FPGA board incorporating the GateMate A1, and it sells the board, the TEG2000-01-P001, on its Web site for €69.00 plus mandatory VAT. Digi-Key offers GateMate A1 FPGA chips for $21.44 in single-unit quantities, making the FPGA a truly low-cost programmable-logic alternative.

Cologne Chip’s GateMate Evaluation Board costs $81.25 from Digi-Key in the US. Image credit: Cologne Chip

With respect to programmable-logic capacity, GateMate FPGAs are comparable in size and capacity to members of the AMD Spartan 7 and Artix 7, Intel Cyclone V, Lattice Certus-NX, and Microchip IGLOO 2 FPGA families. So why pick Cologne Chip’s GateMate FPGAs over these many FPGA alternatives? I can think of three main reasons. First, Cologne Chip touts the fact that GateMate FPGAs are manufactured in Europe, which could present a tariff-free cost advantage for European systems companies. There’s also some regional pride associated with buying European-made semiconductors, and, in today’s environment, supply chains that stretch into Asia no longer seem as bulletproof as they did when globalism was all the rage.

Second, Cologne Chip’s GateMate Evaluation Board and Trenz Electronic’s GateMate board are truly low-cost FPGA boards. It’s hard to find FPGA development boards costing less than $100 these days, but both of these boards qualify.

Third, the GateMate FPGAs appear to cost less than FPGAs from other vendors, at least in unit quantities when purchased from a distributor. For example, an Intel Cyclone V FPGA with 25,000 logic elements costs $68.92 from Digi-Key in single-unit quantities while the GateMate A1 FPGA costs $21.44 from the same distributor in single-unit quantities. However, unit quantity pricing is rarely representative of negotiated volume pricing deals for production, so caveat emptor (let the buyer beware). Perhaps you can think of additional reasons to pick GateMate FPGAs over the alternatives. If so, please feel free to leave those reasons in the comments below.

In the end, it’s great to see another semiconductor vendor dipping a toe into the FPGA arena. Competition has always been good for the FPGA market. Speaking of which, Intel PSG, the FPGA segment of Intel’s chip business, will be announcing its independence and, presumably, its new name on February 29. I’m sure that the company picked that date, a leap day of a leap month of a leap year, to symbolize the leap back into the FPGA manufacturing pool as an independent semiconductor vendor, separate from Intel, which bought Altera in 2015 and renamed it Intel PSG. After nine years, the FPGA company formerly known as Altera will once more be independent of House Xeon. I wonder what they’ll call the new FPGA company. Any guesses?

References

GateMate and Cologne Chip, Adam Taylor, Adiuvo Engineering

GateMate FPGA Tool Chain, Adam Taylor, Adiuvo Engineering