Category: EDA
EDA
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Pulsic Adds Guided Flows
Pulsic has been gradually taking their technologies and turning them into flows. We saw that last year with their planning tools; now place and route…
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Optimizing Power at the Architecture Level
When Mentor handed their flagship HLS product, Catapult C, to Calypto almost a year ago, there were a lot of questions about the move. There…
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2 Spicey?
Tanner just announced the integration of Berkeley Design Automation’s (BDA’s) FastSPICE into their flow. You may remember Tanner as a company that does things their…
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Powering Up Power Analysis
Apache has just released their latest RedHawk version, RedHawk-3DX. In it they’ve focused on areas of growing importance for power: 3D ICs, working at the…
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FPGA Prototype Debug Access
When tracing events on any kind of system, it’s always faster to go local: the farther away the data has to go, the slower it…
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High-Sigma Simulations
We’ve noted before that the meaning of “corners” is much less obvious for analog circuits than it is for digital. Solido noted in a recent…
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Emulator in the Cloud
The other day we noted the launch of Mentor’s Veloce2. There’s one other angle to their release that sidestepped the main announcement. And that is…
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New Emulator Help
Emulators are becoming more important for chip verification. While they used to be valued for in-circuit emulation (ICE) – real-worldish implementations of pre-mask hardware, the…
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14 nm Waking Up
Even as we talk about the Common Platform Alliance’s 14-nm plans, others are also out there putting 14 nm into play. In March, imec announced…
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Another 3 from Springsoft
On the heels of their Verdi3 announcement, Springsoft continues its triplication, now with Laker3. They position Laker as the “best established interoperable custom design flow.”…