Category: EDA
EDA
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Analysis by Braille
As a technology, JTAG (or IEEE 1149.1) has been leveraged a lot of ways to do a lot of things that may not have been…
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More Accurate I/O Models
I/O models have become increasingly important as we’ve moved from dumb 5-V-swing full-rail CMOS I/Os (remember those?) to the tight, sensitive kinds of I/Os needed…
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Catapult C Changes Hands
High-level synthesis (HLS), somewhat synonymous these days with electronic system-level (ESL) design , has been a bloody business. Companies have come and, mostly, gone over…
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IC Manage Fires Back
So… the Methodics/IC Manage saga continues. Last week’s revelations must have caught them somewhat unprepared, so it took them some more time to provide a…
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The Veil is Lifted on Methodics.Com
You may remember something of a kerfuffle about Methodics, which uses the methodics-da.com domain, finding that a page at methodics.com that said that Methodics was…
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The Clouds Converge
We’ve been watching the cloud computing space, and Synopsys has been playing a visible role in exploring the public cloud for compute resource elasticity during…
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The Old Switcheroo
Way back in 2004, during the Vice Presidential debate, Dick Cheney urged listeners to go to “factcheck.com” to confirm that the campaign spin-checking organization would…
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Sorting Through the Rubble
Roughly a year ago we talked about Vennsa’s OnPoint tool for identifying what went wrong during verification when something goes wrong. I got an update…
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Custom Chip Planning
Digital designers have had semi-automated design flows for a long time; custom and analog designers, not so much. Pulsic recently announced that they’re taking some…