Category: EDA
EDA
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Chip Design Tweaker
Last-minute chip design changes are always unfortunate, whether right before cutting masks or, worse yet, after you get silicon back. Some major tool environments provide…
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Another Way to Test Your 3D ICs
A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D…
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New Tools for Managing IP
IP can be a pain in the butt. Any large company will presumably have tons of IP, some from inside, some from outside, being used…
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Switching Classes
High-level synthesis (HLS) has been all about C (or C++) to RTL. But when you’re validating your algorithm, it’s easier to work at the TLM…
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End-to-End Signal Analysis
When two chips talk to each other, they do so over a convoluted path that involves signals leaving a driver, going to a pad, up…
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Home-Brewed Emulators
When you need to verify test suites that drag on for millions (or billions) of clock cycles, it really helps to run them on some…
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A New 3D IC Manager
When Imec and Atrenta recently announced a design flow for planning and routing signals between different stacked ICs, I thought, “Wait, I’ve seen this before,…
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Allocating Spectrum
A couple years ago, in an article about clock-generated noise, we talked about Teklatech’s power-shaping feature, which, at the time, was designed to smooth out…
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Take it Outside
As flexible as FPGAs are, you would think that you could stuff debug logic in there to probe around the internals and figure out what’s…
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Quicker LTE Validation
Each new communications protocol adds to the complexity of its predecessor, and the 3GPP-LTE cellular standard is no exception. According to Synopsys, there are more…