Category: EDA
EDA
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Stop Repeating Yourself
You may recall a while back – actually, a good while back – we looked at parasitic extraction tools and contrasted the field solver approach…
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Veridae Proliferates
Last fall we took a look at Veridae’s Clarus debug tool. At the time, it was positioned to handle SoCs and FPGAs, including multi-FPGA prototype…
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Greater Certitude
About two years ago, we looked at a new product from SpringSoft, Certitude, inherited through the acquisition of Certess. SpringSoft has just announced some improvements…
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Xilinx’s Crossover
Xilinx announced their new Zynq family a while back, and now they’re working the positioning to further clarify why it’s different from past processor+FPGA combo…
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Get Wreal
When analog design discussions turn to simulation, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I…
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DDR3 System On-and-Around the Chip
We saw the other day that Cadence was being aggressive with the memory controller IP from their Denali side. They’re actually trying to create a…
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In a Different Field
Part of the Cadence Allegro release features a new field solver they’ve included for power delivery network (PDN) analysis, the product of collaboration with the…
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Going Up
It’s always helpful when complex new technological ideas can be related to everyday concepts. So when I heard about “test elevators,” proposed by imec, for…
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Making the Line Move Faster
No one likes standing in line, but if you’re going to be doing any serious parallel processing, you’ll run into many queues as a way…
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28-nm NVM Lives
A couple years ago we looked at the possibility that non-volatile memory (NVM) might have a limited future. Given that the main physical mechanism of concern…