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Category: EDA

EDA

  • Detailed RTL Power Analysis

    If you want to minimize the power consumption of your system, you can’t wait until you have your design reduced to gates. Yeah, you can…

  • New Toy in the Sandpit

    EDA Playground is a neat idea. From your browser you can simulate chunks of SystemVerilog, Verilog, VHDL, C++, SystemC and other HDLs, using Aldec and…

  • Cadence’s Faster Debug Idea

    Cadence is proposing a new way to approach debug. It’s almost an obvious way, except that this isn’t how most debug has traditionally been done.…

  • Faster NoC Tuning

    In a sleepy little town of 4 or 5 houses, you can be pretty informal about how mail arrives at its destinations. People can come…

  • Driving ADAS

    ARM reckons that the computational power in your car is set to increase by 100X in the next ten years, mainly through the growth of…

  • Requirements Modeling and Simulation

    So you’re working on a design… Are you sure you’re building what was intended? Yes, you’re building what they asked for… or, at least, what…

  • Tanner to Join Mentor: Outsider Gets a Crew

    Way back in 2009, we took a look at Tanner – an EDA company marching to its own beat. They always seemed – and continue…

  • Synopsys and Leading-Edge Litho

    While wandering the halls of SPIE Advanced Litho, I had a conversation with Synopsys’s Tom Ferry about their focus for the leading edge of lithography.…

  • Universal Verification Stimulus Format

    We used to be ok with the verification silos we grew up with. You’ve got your simulation guys over here helping with circuit and block…

  • What Does a 5nm Transistor Look Like? I

    Synopsys and Imec recently announced that they’d be collaborating on TCAD activities for the 5nm node. Yup. 5nm. You can count ‘em on one hand.…