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Category: EDA

EDA

  • Continued FinFET Roll

    The Synopsys Users’ Group scheduled a panel session on FinFETs at their recent session. This is consistent with pretty much every EDA company providing FinFET…

  • 3D-IC Planning

    During Cadence’s recent CDNlive event, I had a discussion with Kevin Rinebold to talk about 3D-IC planning and design. Actually, it’s more than that, covering…

  • The Worst Two Answers

    You’re an upstanding product marketing guy, and you want to validate your company’s product ideas with customers and potential customers. So you go get in…

  • 20 to 14: Less Bad Than You Thought?

    Conventional wisdom should suggest the following points: Each new process node affects all layers Moving to FinFETs will be a big change for designers Turns…

  • Tools vs IP

    All of the major EDA companies have had IP. Synopsys started with DesignWare before IP was a real concept; Mentor had IP associated with consulting…

  • MORE Lawyers, Please!

    In response to Dick Selwood’s recent article “Lawyers, Bankers, and Engineers”, I want to take a different (and perhaps controversial) stand:  We need MORE lawyers.…

  • A New Verb for Hardware Engineers

    Ever since malloc() (and it’s other-language counterparts), software engineers have had an extra verb that is foreign to hardware engineers: “destroy.” Both software and hardware…

  • Algorithms or Methodologies?

    You see it two to four times a year from each EDA player: “x% Productivity Gains with y Tool!” Cadence recently had such an announcement…

  • It must have been a dead-heat

    Two e-mails plopped in to the in-tray, both with the same time stamp The first was headlined ARM and Cadence Tape Out First 14nm FinFET…

  • Uniting Balkanized Designs

    There used to be a nice, clean division: digital chips were verified using the standard suite of digital verification tools like simulation and formal analysis;…