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Category: EDA

EDA

  • 20-nm Test Enhancements

    ITC is usually the time when the EDA companies announce their coolest test-related advances. While Mentor announced their IJTAG support, Synopsys focused its agenda largely…

  • Breker Tests Multicore

    Earlier this year we were introduced to Breker, a company that generates C tests for stressing SoC architectures and verifying that things work even with…

  • Using Formal to Help Simulation

    While simulation is the granddaddy of verification, there are thorny problems that simulation doesn’t handle well, and formal analysis has gradually come of age over…

  • What’s New at 20 nm

    We talked in a separate piece today about Synopsys’s multi-source clock synthesis technology, but that was only one of several pieces of new technology in…

  • Being Ahead Puts You Further Ahead

    We love the underdog. David slays Goliath. All of that. And we love the myth that hard work and a better idea will always win.…

  • More Efficient Vectors

    In the wake of the UCIS announcement at DAC (which we’ll cover separately later), I sat down with some of Mentor’s functional verification folks to…

  • More Custom Cores

    At DAC, there was a special event for first-time DAC exhibitors to come talk to media folks. Kind of a way for them to get…

  • Constraining Big Designs

    It’s been a while since we took a look at timing constraints (and, in particular, their exceptions). In fact, the exceptions are where things often…

  • Hierarchical Bug Tracking

    Right about the time I was trying to sort through the recent DM tussle, I also happened to be talking to Dassault about their new…

  • Analog Standard Cells

    The annual DAC CEDA luncheon this year featured Stanford EE Dept. chair Mark Horowitz in a discussion of analog abstraction. Which has always been a…