Archives: Chalk Talks
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Verification Made Easy with Memory Models
In this week’s Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today’s SoCs. He’ll explain the differences betweeen…
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PADS VX: Redefining Productivity – Tech Packet
Click the links below to download a free whitepaper with more information about Mentor Graphics PADS Tool Suite. Also, don’t forget to watch our Chalk…
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PADS VX: Redefining Productivity
When it comes to PCB Design, the giant companies don’t get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival…
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Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation
Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can’t expect our synthesis tool to produce the…
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What is Electrically Aware Design?
For years, layout tools have focused on the pins and wires, the “froms” and “tos”, the segments and nets – without considering that they were…
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Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis
Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt…
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Integrating Electronic Design Analysis Upstream, Downstream, and Sideways
PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend…
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Design Control, Data and Comparison with PADS Archive Management
Do you spend too much time archiving your designs, and later searching through archives for just that one project? Are your engineering reviews disorganized? Does…
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Vivado In-System Debug
Today’s complex FPGA designs can be challenging to debug. If you’re debugging in hardware, you need both visibility and control of what’s going on inside…