Archives: Chalk Talks
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Overcome the Challenges of Highly Constrained Designs
Many of today’s high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of…
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100G Ethernet Packet Parsing with Spacetime
Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it’s easy to fall into a design…
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Building a New Type of IP Factory
Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can…
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Cadence Low Power Solution – RTL to GDSII Low Power Design
Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle – from RTL all the way…
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Cadence Tempus Timing Signoff Solution
Achieving timing closure for signoff can be a daunting challenge in today’s complex designs. Meeting timing under all conditions – with the certainty required for…
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It’s the Software, Silly! – Success with FPGA-based Prototyping
Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software…