Archives: News
-
Jasper ActiveProp Automates Assertion-Based Verification for SoC Design
MOUNTAIN VIEW, Calif. – Jan. 27, 2011 – Jasper Design Automation today introduced ActiveProp(tm), an innovative new property synthesis tool that helps accelerate the adoption of assertion-based…
-
Tanner EDA to Address Some of the Key Challenges Facing Analog Designers at DesignCon 2011
MONROVIA, California – January 25, 2011 – At DesignCon 2011, Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal…
-
Synopsys’ DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP
MOUNTAIN VIEW, Calif., Jan. 26, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing,…
-
Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability
WILSONVILLE, Ore., January 25, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced that Fujitsu Semiconductor Limited is now using the Calibre® PERC product for electrical rules…