Is 1 TFLOPS possible on a single FPGA? At 28 nm, Altera’s Stratix V FPGA, with its uniquevariable-precision digital signal processing (DSP) architecture, is equipped to deliver thisperformance level. This architecture combines the implementation efficiency of common DSPfunctions such as fast Fourier transforms (FFTs) and finite impulse response (FIR) with the bestsupport for higher precision and floating-point signal processing.
Watch this 30-minute webcast to learn how:
- Our new fused datapath design flow is the only tool that can synthesize floating-point datapaths within an FPGA
- Our Stratix V FPGAs provides the hardware resources required for TFLOPS performance
- Our extensive library of floating-point intellectual property (IP) cores streamline the DSP design process
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