At DVCon, Calypto Demonstrates High Level Synthesis, Power Optimization and Electronic Design Equivalence Checking; Participates in Multi-Core SoC Tutorial

Who/What

At the Design Verification Conference (DVCon), Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, will demonstrate its products – Catapult® HLS (High Level Synthesis), SLEC® (Sequential Logic Equivalence Checking) andPowerPro®. These products enable ESL design, dramatically improve design quality, and reduce the power consumption of SOCs.

Bryan Bowyer, Senior Design Specialist, Calypto will participate in a tutorial on the Design & Verification of Platform-Based, Multi-Core SoCs with ARM and Mentor Graphics. The tutorial covers the process of defining an SoC system based on platform subsystem IP, the development and integration of hardware acceleration blocks, analyzing system performance criteria, verification of the SoC functionality, the development and validation of software using virtual prototyping and acceleration technology and verification from block to SoC to full system. 

What’s New

Calypto’s High Level Synthesis product (HLS), Catapult Synthesis now includes bus interface libraries that connect its hardware subsystems with AMBA® AXI™ bus interfaces. The libraries include master and slave interfaces with both Transaction Level Modeling (TLM) and HLS views, which allows easy interplay between a TLM 2.0 platform and HLS implementation flow without degrading simulation performance or hardware quality. 

When/Where

Exhibit & Demonstrations

Tuesday, Feb. 28, 3:30-6:30pm

Wednesday, Feb. 29, 4:30-7:00pm

Booth # 505

Tutorial

Thursday, March 1, 8:30am – 12:00pm

Design & Verification of Platform-Based, Multi-Core SoCs

DoubleTree Hotel, San Jose, California

For More Information

For more information about Calypto, please visit at www.calypto.com.

For more information about DVCon, please visit www.dvcon.org.

About Calypto

Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.

Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE?SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, and Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.

More information can be found at www.calypto.com.