Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.
More Articles
-
Sticking With their Story: Zeno Demonstrates 1T SRAM at Leading Nodes
Let’s face it: We’re addicted to SRAM. It’s big, it’s power-hungry, but it’s fast. And no matter how much we…
-
Bill Godbout Perishes in Northern California’s Camp Fire
People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the…
-
Costs for Sub-20nm Wafers put Another Nail in Moore’s Law’s Coffin
IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts…
Leave a Reply
You must be logged in to post a comment.