High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently addressing the subsequent increase in system bandwidth by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This challenge includes targeting lower bit error ratios (BERs) and ensuring signal and power integrity while maintaining power efficiency and optimizing design productivity. This white paper explores transceiver architecture in Altera® 28 nm FPGAs for applications at 10 to 28 Gbps, and highlights the architectural advantages for making high performance systems with low BER.
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