De-Risk Yield Manufacturing Ramp-up with Veloce DFT App

Get DFT off the critical path on your next chip design. In this episode of Chalk Talk, Amelia Dalton chats with Jean-Marie Brunet of Mentor Graphics about how you can use emulation to significantly improve your DFT productivity. 

Click here to download a whitepaper entitled “Accelerating Design-For-Test Pattern Simulation.”