An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28nm FPGAs

Altera recently introduced a floating-point design flow intended to streamline the process of implementing floating-point DSP algorithms on Altera FPGAs, and to enable those designs to achieve higher performance and resource usage efficiency than previously possible. BDTI performed an independent evaluation of the power consumption and energy efficiency of Altera FPGAs for demanding floating-point DSP applications. This white paper presents BDTI’s findings from this evaluation.