Archives: Articles
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Gate First vs. Last
There’s been a war out there, and it goes something like this: “It can’t be done the old way anymore. We need to use the…
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Black Helicopters
John (a real engineer, but not his real name) sat in his office staring at his workstation monitor. John’s door was closed. It was always…
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System-Level Debugging and Monitoring of FPGA Designs
This white paper describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device…
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Building a Custom Verification GUI with System Console
Want to know how to easily create GUI dashboards to interact with your design? Watch this new demo to learn how to: Add run-time visibility…
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There Goes the Neighborhood
Anyone who’s ever done any serious remodeling of their home knows the big decision. At some point, wouldn’t it really be easier just to mow…
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Optimize Your 28-nm FPGA Design for Maximum Performance
Want the best performance from your 28-nm FPGA design? Find out how you can make optimal use of Altera’s 28-nm architecture to maximize your system…



