Archives: Articles

  • What “Is” Is

    What “Is” Is

    We’ve created a special domain for legal issues in this country. If it looks like a lawyer might have to get involved, the rest of…

  • Scalable Smart Debugging With ZeBu-Server

    Billion Gates got you down?  Over the years, Moore’s Law has made finding a bug in our designs harder than ever as our gate counts…

  • (un)Rolling with the Times

    (un)Rolling with the Times

    A HW engineer and an embedded SW developer, who are slated to work together on a common project, strike up a conversation at the proverbial…

  • Lessons from Fukushima

    Lessons from Fukushima

    In August a group of experts on risk, safety engineering, and related matters looked at the Fukushima Daiichi nuclear power station disaster to see what…

  • Faster Floating-Point

    Faster Floating-Point

    We’ve done dozens of articles about how awesome FPGAs are for signal processing applications – with a measure of salt.  We’ve pointed and laughed as…

  • Minding the Gap

    Minding the Gap

    Assumptions are always dangerous, but there’s one reasonably safe assumption you can make about our IC-related topics: the underlying material is most likely silicon. Silicon…

  • Anatomy of a Software Code Audit Process

    Anatomy of a Software Code Audit Process

    Software has become a major component of products that are produced by most technology companies and is rarely written from scratch. Resourceful software development organizations…

  • Not Much New Under the Sun

    Not Much New Under the Sun

    These are not the times for DIY or NIH if you can help it. More and more is expected of fewer and fewer people, so…

  • When Programmers Rule the World

    When Programmers Rule the World

    “Their talents did not quite run to scholarship.” This was Susanna Clarke’s polite way of describing a pack of idiots. Or more charitably, people who…

  • An Independent Analysis of Altera’s FPGA Floating-Point DSP Design Flow

    Altera has developed a new floating-point design flow intended to streamline the process of implementing floating-point digital signal processing algorithms on Altera FPGAs, and to…