Archives: Articles
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GiDEL Announces the Availability of TotalHistoryâ„¢ a New Level in ASIC Prototyping and FPGA Debug
Kane Computing are pleased to announce that GiDEL has recently launched TotalHistory™, the most advanced debugging feature available in today’s ASIC Prototyping solutions and FPGA…
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GiDEL Announces Its Third-Generation ASIC Prototyping Systems Based on on Altera’s Stratix IV E FPGAs
Kane Computing are pleased to announce that GiDEL recently launched the PROC_SoC3-4S™ and the PROC_SoC10-4S™ ASIC Prototyping Systems utilizing the industry’s largest FPGAs – Altera’s…
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From Conductor to Semi
“So why do you think you’re right for this job? “Well, it’s pretty much exactly what I’ve done for the last 10 years. We were…
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Timing Closure in 2011
[Editor’s note: Atrenta’s Ron Craig and Magma’s Bob Smith got together to provide two viewpoints on what is going to be most important for timing…

