Archives: News
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Thursday is Training Day Tradition Continues at the 54th Design Automation Conference
High quality training in three tracks on SystemVerilog, UVM, Python and C++ with new Lunch and Learn taster session on Wednesday LOUISVILLE, Colo. – May…
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Cadence Expands JasperGold Platform for Advanced Formal-Based RTL Signoff
JasperGold Formal Verification Platform’s new Superlint and Clock Domain Crossing Apps reduce logic designer’s IP development time by up to four weeks SAN JOSE, Calif.,…
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AVX is Now Sampling the First-Ever Combined IDC/Press-Fit Wire-to-Board Connection System
The new 53-8702 Series combines the two most reliable contact technologies in the automotive industry in a single package to deliver robust, double-ended, cold-welded, &…
