Archives: News
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50th DAC Announces First Ever Training Day to Keep EDA Updated on Latest Design Techniques
LOUISVILLE, Colo. –– May 20, 2013 –– The 50th Design Automation Conference (DAC), the premier conference devoted to electronic design, design automation, IP and embedded systems and software,…
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Aldec launches Spec-TRACER™
Certification Together International Conference (CTIC), Toulouse, France – May 20, 2013 – Aldec, Inc., CTIC Platinum Sponsor and pioneer in mixed-language simulation and advanced design tools for FPGA and…
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COMSOL Multiphysics 4.3b Offers Breakthrough Analysis Tools
BURLINGTON, MA — COMSOL Inc., the leader in multiphysics simulation software, today announced the release of major new additions to the COMSOL simulation platform. The…
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Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs
Sunnyvale, Calif. – May 20, 2013– Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex system-on-chip (SoC) designs, has…
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Berkeley Design Automation Announces Analog Characterization Environment
SANTA CLARA, CA, — May 16, 2013— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced the immediate availability of…
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KACST (King Abdulaziz City for Science and Technology) launches WaferCatalyst Silicon prototyping services
Riyadh, Kingdom of Saudi Arabia, May 18th, 2013 – King Abdulaziz City for Science and Technology (KACST), the Kingdom of Saudi Arabia’s National Science Agency &…
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Cadence Introduces the Tempus Timing Signoff Solution, Delivering Unprecedented Performance and Capacity in Design Closure and Signoff
SAN JOSE, CA–(Marketwired – May 20, 2013) – Cadence Design Systems, Inc. (NASDAQ: CDNS) HIGHLIGHTS:Cadence Design Systems, Inc. (NASDAQ: CDNS) The Tempus Timing Signoff Solution yields up to an order…