Lower Power and Boost System Bandwidth on 28nm FPGAs

It’s a challenging balancing act to meet growing bandwidth demands without increasing cost or power consumption. And it’s probably a challenge you know well if you’re designing high-end systems in areas such as communications, broadcast, military, and computer/storage. Achieve the right balance with Altera’s Stratix^® V FPGAs, which deliver breakthrough bandwidth, reduced cost, and the lowest total power.

Watch this 40-minute webcast to get more details about innovations in Stratix V FPGAs that address bandwidth and power challenges.

You’ll learn about:

• 28-nm process and architectural innovations that lower static power by 44 percent
• 28-nm power-efficient transceivers that run at data rates up to 28 Gbps and deliver 50 percent lower power per channel
• Embedded HardCopy^® Blocks and various intellectual property (IP) blocks that enable higher integration for lower power and cost
• Easier board design at lower power and lower cost
• Software power optimization, including clock gating algorithms, for 18 percent lower dynamic power