What: Agilent Technologies and Aldec will present a session on how to validate a digital signal processing algorithm for both floating and fixed point levels. Attendees will gain insight on a cross-domain approach to traditional FPGA design flow and learn how to validate FPGA designs for leading edge wireless and radar systems with a system-level simulation tool integrated into the traditional hardware design flow.
When:    2:00 PM — 4:00 PM, Wed., June 5, 2013Â
Where: Â Design Automation Conference, Austin Convention Center, Room 17AB
Additional Information:Â Â Â Â Â Â Â Â www.agilent.com/find/eesof.
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