Archives: News
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Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process
San Jose, Calif., July 13, 2016 ?Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its implementation and signoff tools have achieved certification on the…
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Synopsys TetraMAX II Speeds Test Generation for STMicroelectronics SoC Designs
MOUNTAIN VIEW, Calif., July 12, 2016 /PRNewswire/ — Highlights: Evaluation of TetraMAX II demonstrated an order of magnitude speedup in runtime Achieves significant test-pattern-count reduction without impacting…
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Toshiba Plans Deployment of Synopsys TetraMAX II on Upcoming SoC Design
MOUNTAIN VIEW, Calif., July 12, 2016 /PRNewswire/ — Highlights: Thorough evaluation of TetraMAX II demonstrated significant reductions in both pattern count and runtime without impacting test coverage…
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IRT Nanoelec and CMP Announce World’s First Multi-Project Wafer Service with Silicon Photonics on 310nm SOI Platform
GRENOBLE, France – 11 July, 2016 – IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro and nanoelectronics, and CMP, Circuits Multi-Projets®, a service organization in ICs…
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Keysight Technologies Introduces Industry’s First All-in-One Software for R&D Engineers Designing, Evaluating 5G Candidate Waveforms
Highlights: Simplifies the building of test systems with wideband channels at the transmitter, receiver, or both Facilitates complex calibration of RF to millimeter-wave measurement systems…
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Imec and Synopsys Collaborate on Interconnect Resistivity Model to Enable Early Screening of Interconnect Technology Options at Advanced Nodes
MOUNTAIN VIEW, Calif., July 11, 2016 — World-leading nano-electronics research center imec and Synopsys, Inc. (NASDAQ: SNPS) today announced an interconnect resistivity model to support…